Advanced FPGA-based systems design techniques for wearable sensor applications

Abstract

The concept of a Smart Home has evolved remarkably over the past few decades, introducing the monitoring of human activity in the home environment for health management through sensors connected to the Internet, whose data can be accessed by the various professionals involved (e.g. medical doctors, caregivers, relatives) and the users themselves. At the D2Lab research group of Electronics Engineering at the University of Parma, a new home monitoring system has been developed to enable the behavioral analysis of the users inside their home. Its working principle relies on a set of battery-powered sensors connected to an Internet cloud service used for the analytics to provide a set of daily, weekly or monthly behavioral analyses to the user. This is required to highlight variations on user’s macro- and long-term patterns (e.g. a decrease in mobility), and to act with specific prevention programs. The system relies on the Wi-Fi connectivity, which features a wider area coverage and can exploit a standard Wi-Fi home router (quite often already present in the homes) for the Internet connection. The result is a more scalable and less expensive final implementation. This comes at the expense of an increased power consumption, which may harm the sensors' battery lifetime. For this reason, dedicated sensor platforms have been designed for low-power operation even on Wi-Fi connectivity. The system is composed of four environmental sensors, which have been subsequently integrated with a prototype of wearable sensor for Human Activity Recognition (HAR) to enrich the behavioral analysis. The design of the final device requires energy-aware techniques, which consist in a low usage the Wi-Fi radio usage possibly achieved by moving a part of the computation from the cloud to onboard, so to upload just the final activity of the user. This is the context of this thesis, which started with the performance assessment of two sets of the four environmental sensors: a magnetic contact, an armchair/bed, a Passive InfraRed (PIR), and a toilet proximity sensor. The first set of sensors was used to evaluate stand-by battery lifetime in laboratory while the second one was placed in a real home environment to evaluate real battery lifetime. After two months of testing, only the toilet proximity sensors ran out of battery. For the other sensors, the laboratory set showed a residual charge of about 46%, while in the home environment this value was 34%. In some cases, the network could undergo connectivity issues; in these situations, dedicated operating cycles were introduced to reduce the impact on the battery lifetime. This lead to a reduction in the current absorption of 42% in the case of Wi-Fi network absence and of 91% in the case of a lack of Internet connectivity. In the rest of the thesis, the focus is on the wearable sensor. The work started from a prototype already defined, which has been used as the platform to build a dataset of 7 activities (walking, stand, sitting-down, stay seated, standing-up, running, climbing stairs down, climbing stairs up, lie-down) to build a machine learning algorithm for HAR. A core algorithm has been identified which can be used in both a Support Vector Machine (SVM) classifier (used in this work) and, in general, as the activation function of neural networks algorithms nodes. For the selection of the SVM algorithm in which to introduce the core, different training phases has been carried with the MathWorks Classifican Leaner tool, and the Cubic kernel version demonstrated the best accuracy of 93.2%. The selected algorithm has been then elaborated for FPGA implementation exploiting the model-based design approach, implemented with Simulink for the design phase, and with the HDL Coder code for automatic code generation (VHDL). The VHDL code has been implemented on a Altera Cyclone IV FPGA, resulting in a resources usage of the 88% of the Logic Elements, the 100% of the Multipliers, and the 15% of the Memory blocks. After this, a VHDL timing simulation has been carried out to evaluate the correctness of the output value. The result of this step turned to be negative, since the verification of the output always ended with a failure. Two solutions have been identified as the candidates to solve this issue. The first one is the introduction of pipeline stages inside the architecture. However, this practice introduced a new issue related to the accumulators (i.e. the objects performing the summation of a vector) architectures, which would have forced to slow down the whole system with additional data delays. For this reason, the state-of-the art Delay Buffering accumulator has been investigated and implemented on a Xilinx Artix 7 and an Altera Cyclone 10 LP FPGAs with the same aforementioned model-based design approach. Results were compared with the available Simulink IP accumulator, demonstrating a reduction of about 95% in both area and time. Other comparisons have been carried out with the literature and with the Vivado IP, confirming the choice of architecture. The accumulator has then been integrated in the Cubic SVM for performance assessment and oscilloscope measurements, furhter conferming the previous results. The second solution evaluated to solve the timing issues is a replacement of the IEEE 754 32-bit floating-point format used for the computations inside the system with the novel Posit format. A study has been carried out using the model-based design approach on a Posit multiplier use case, which has been improved from the state-of-the art with a modified version derived from the Vedic architecture. The Vedic architecture is at the heart of the Vedic multiplier for integer numbers and, differently from traditional binary multiplication algorithms, features a high modularity. This has been exploited and introduced in the Posit multiplier to replace the exponents sum and fractions multiplication with a unique, synergistic block. The proposed solution has been compared with a traditional Posit multiplier based on a Booth Radix-4 multiplier for the fractions. The comparison has been carried out in terms of Posit numbers bit length (i.e. 8, 16 and 32 bits) and pipeline stages introduced inside the system (i.e. from 1 to 3 for the 8 and 16 bits, and 1 to 5 for the 32 bits) and results show a performance improvement of up to 26.3% of the area-time product of the proposed solutions.